Semiconductor chip manufacturing business

Manufacturing semiconductor chips is a highly complex process and equipment needed for it is still more complex. Applied Materials’ Silicon Systems group segment is a leader in this niche industry. It generated around $5.97 billion in revenues in 2014 through this business which had $1.39 billion operating income. The net capital expenditure was just $134 million and total assets were $5.5 billion. The ratio of Operating income to total assets was ($1.39 / $5.97) = 23%. This is sign of a business with great Economics because of the large moat it possesses . Following is an excerpt from the company’s latest 10-K report that provides details of the Semiconductor equipment manufacturing business. As of Dec-12 2014 the company had over 33,000 semiconductor chip manufacturing systems all over the world. The revenue generated from servicing these machines in 2014 was $2.2 billion with operating income of $573 million.

Most chips are built on a silicon wafer base and include a variety of circuit components, such as transistors and other devices, that are connected by multiple layers of wiring (interconnects). Applied offers systems that perform various processes used in chip fabrication, including chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, electrochemical deposition (ECD), rapid thermal processing (RTP), ion implantation, chemical mechanical planarization (CMP), epitaxy (Epi), wet cleaning, atomic layer deposition (ALD), wafer metrology and inspection, and systems that etch or inspect circuit patterns on masks used in the photolithography process. Applied’s semiconductor manufacturing systems are used by integrated device manufacturers and foundries to build and package memory, logic and other types of chips.The majority of the Company's new equipment sales are for leading-edge technology for advanced 2X nanometer (nm) nodes and smaller dimensions. HOW A CHIP IS BUILT? To build a chip, the transistors, capacitors and other circuit components are first created on the surface of the wafer by performing a series of processes to deposit and selectively remove portions of successive film layers. Similar processes are then used to build the layers of wiring structures on the wafer. As the density of the circuit components increases to enable greater computing capability in the same or smaller physical area, the complexity of building the chip also increases, necessitating more process steps to form smaller transistor structures and more intricate wiring schemes. Advanced chip designs require more than 500 steps involving these and other processes to complete the manufacturing cycle. Today's advanced interconnects are made using copper as the main wiring material. Copper has low resistance and can carry a large amount of current in a small area, which allows signals to travel quickly. Applied is a leading supplier of systems for manufacturing copper-based interconnects, including equipment for depositing, etching and planarizing these multi-layer structures.To increase the speed of interconnect signals even further, low dielectric constant (low k) films are used to insulate the copper wiring. Applied provides systems for depositing low k dielectric films that enable higher device performance and longer battery life. The transistor is another key area of the chip where semiconductor manufacturers are improving their device designs to enhance performance. Applied has technically-advanced products for building smaller and faster transistors. One method of enhancing chip performance is strain engineering, a technique that stretches or compresses the space between atoms, allowing electrical current to flow more quickly. Multiple strain films are typically used in advanced devices since they have an additive effect on increasing transistor speed. Applied has systems to enable these applications using CVD and epitaxial deposition technologies. Major chipmakers are integrating high dielectric constant (high-k) and metal materials and processes in their transistor gate structures to increase chip performance and reduce power consumption. Applied has fully characterized processes for building these high-k/metal gates. These solutions include an integrated gate stack tool that combines multiple critical steps in a single system, including a portfolio of metallization technologies using CVD, ALD and PVD processes. 3D ICs : To address the need for higher performance in a smaller space driven by new consumer products, a new type of chip packaging at wafer level is emerging, which enables three-dimensional (3D) ICs. Providing greater functionality in a smaller footprint, 3D ICs stack multiple chips together and electrically connect them using deep holes, called through-silicon via (TSV) structures. Applied has production-proven systems and processes required for advanced packaging, including etch, CVD, PVD, ECD, wafer cleaning and CMP systems. Most of Applied’s semiconductor equipment products are single-wafer systems with multiple process chambers attached to a base platform. This enables each wafer to be processed separately in its own environment, allowing precise process control, while the system’s multiple chambers enable simultaneous, high productivity manufacturing. Applied sells most of its single-wafer, multi-chamber systems on eight basic platforms: the Endura®,, Centura®, Producer®, CentrisTM, Reflection®, Raider®, VIISta® and Vantage® platforms. These platforms support ALD, CVD, ECD, PVD, etch, ion implantation, and RTP technologies. Over time, the semiconductor industry has migrated to increasingly larger wafers to build chips. The predominant or common wafer size used today for volume production of advanced chips is 300 millimeter (mm), or 12-inch, wafers. Applied offers 300mm systems through its Silicon Systems Group segment. In addition, Applied offers earlier-generation 200mm systems, as well as products and services to support all of its systems, which are reported under its Applied Global Services segment. Deposition – In fabricating a chip Deposition is a fundamental step in fabricating a chip. During deposition, layers of dielectric (an insulator), barrier, or electrically conductive (typically metal) films are deposited or grown on a wafer. Applied Materials provides equipment to perform four types of deposition: ALD, CVD, ECD and PVD. In addition, Applied’s RTP systems can be used to perform certain types of dielectric deposition. Atomic Layer Deposition - ALD is an advanced technology in which atoms are deposited one layer at a time to build chip structures. This technology enables customers to fabricate thin films of either conducting or insulating material with uniform coverage in nanometer-sized structures. One of the most critical areas of the transistor is its gate, which is built by depositing layers of dielectric films. At the 22nm node and below, these film layers are so thin that they must be atomically engineered. The Applied Centura Integrated Gate Stack system features advanced ALD technology that builds ultrathin high-k film layers less than 2nm in thickness. Chemical Vapor Deposition - CVD is used to deposit dielectric and metal films on a wafer. During the CVD process, gases that contain atoms of the material to be deposited react on the wafer surface, forming a thin film of solid material. Films deposited by CVD may be silicon oxide, single-crystal epitaxial silicon, amorphous silicon, silicon nitride, dielectric anti-reflective coatings, low k dielectric (for highly-efficient insulating materials), aluminum, titanium, titanium nitride, polysilicon, tungsten, refractory metals or silicides. Applied offers the following CVD products and technologies: The Applied Producer CVD platform — The Producer high-throughput platform features Twin-Chamber® modules that have two single-wafer process chambers per unit. Up to three Twin-Chamber modules can be mounted on each Producer platform, giving it a simultaneous processing capacity of six wafers. Many dielectric CVD processes can be performed on this platform. The highest productivity model of this system is the Applied Producer GT, which features fast wafer handling performance and compact design. Low k Dielectric Films — Low k dielectric materials are used in copper-based chip designs to further improve interconnect speed. Using conventional CVD equipment, the Applied Producer Black Diamond® family of low k systems provides customers with a proven, cost-effective way to integrate a variety of low k films into advanced interconnect structures. The Company's latest third-generation low k technologies are featured on the Applied Producer Black Diamond 3 system and Applied Producer Nanocure 3 system. In addition, the Company offers its Applied Producer OnyxTM process, an innovative film treatment that optimizes the molecular structure of low k films. Together, these products are designed to enable smaller, higher performance and more power-efficient devices at 22nm and below. Lithography-Enabling Solutions — Applied offers several technologies on the Producer system to help chipmakers extend their current 193nm lithography tools, including a line of Applied APF® (advanced patterning film) films and Applied DARC® (dielectric anti-reflective coating) films. Together, they provide a film stack with the precise dimensional control and compatibility needed to cost-effectively pattern nano-scale features without additional integration complexity. Gap Fill Films — There are many steps during the chipmaking process in which extremely small and deep, or high aspect ratio (HAR), structures must be filled void-free with a dielectric film. Many of these applications include the deposition of silicon oxides in substrate isolation structures, contacts and interconnects. Applied's most advanced gap fill system is its Applied Producer Eterna™ FCVD™ system. Targeted for 20nm and below chips, the Eterna system delivers a liquid-like film that flows freely into virtually any structure to provide void-free dielectric fill. Strain Engineering Solutions — The Applied Producer HARP™ system plays a key role in enhancing transistor performance, enabling chipmakers to boost chip speed by depositing strain-inducing dielectric films. Offering the industry’s first integrated stress nitride deposition and ultraviolet (UV) cure solution, the Applied Producer Celera CVD delivers benchmark levels of high-stress tensile silicon nitride films. The Company also offers the Applied Centura SiNgenPlus low pressure CVD system for low temperature silicon nitride films. Used together, and in conjunction with silicon germanium (SiGe) films using Applied’s epitaxial deposition technologies, these systems can provide additive strain engineering benefits. Through-Silicon Via Films — Applied offers products for TSV fabrication, including the Applied Producer InVia™ system. This product uses an innovative process to deposit the critical oxide liner film layer in HAR TSV structures, enabling robust electrical isolation of the TSV, which is vital for reliable device performance. For applications where higher temperatures can damage the manufacturing process, the Applied Producer Avila™ CVD system and Applied Producer OptivaTM CVD system allow high-quality dielectric film deposition at stable substrate temperatures. 3D NAND and FinFET Films — 3D NAND requires deposition technology for vertical gate formation and complex patterning applications. Applied offers products for FinFET and 3D NAND fabrication, including the Applied Producer XP PrecisionTM CVD system released in 2014, which addresses the deposition challenges presented by vertical 3D architectures. Designed for high-volume manufacturing, the XP Precision system combines production-proven Producer CVD technology with more efficient, faster processing chamber technology. Copper Interconnect Encapsulation Solutions — In 2014, Applied introduced its Endura VoltaTM CVD Cobalt system for encapsulating copper interconnects in logic chips smaller than the 28nm node. The system deposits a conformal cobalt liner and selective cobalt capping layer to provide complete enclosure of copper lines, improving reliability while reducing yield-limiting issues. Epitaxial Deposition — Epitaxial silicon (epitaxy or epi) is a layer of pure silicon grown in a uniform crystalline structure on the wafer to form a high quality base for the device circuitry. Epi technology is used in an increasing number of IC devices in both the wafer substrate and transistor areas of a chip to enhance speed. The Applied Centura Epi system integrates pre- and post-epi processes on the same system to improve film quality and reduce production costs. This system is also used for SiGe epi technology, which reduces power usage and increases speed in certain types of advanced chips. For emerging transistor designs, the Applied Centura RP Epi system offers selective epi processes to enable faster transistor switching through strain engineering techniques. Polysilicon Deposition — Polysilicon is a type of silicon used to form portions of the transistor structure within the IC device. The Applied Centura Polygen™ LPCVD system is a single-wafer, multi-chamber product that deposits thin polysilicon films at high temperatures to create transistor gate structures. To address the challenging requirements of shrinking gate dimensions, the Applied Centura DPN Gate Stack system integrates chambers for decoupled plasma nitridation (DPN), RTP anneal, and polysilicon deposition on one platform to enable superior film quality and material properties. Tungsten Deposition — Tungsten is used in the contact area of a chip that connects the transistors to the wiring circuitry. In aluminum-based devices, tungsten is also used in the structures that connect the multiple layers of aluminum wiring. Applied has two products for depositing tungsten: the Applied Centura Sprint® Tungsten CVD system and the Applied Centura iSprint® ALD/CVD system which provide tungsten filling capability to 20nm and below. Electrochemical Deposition ECD is a process by which metal atoms from a chemical fluid (an electrolyte) are deposited on the surface of an immersed object. One application is to deposit copper in interconnect wiring structures. This process step follows the deposition of barrier and seed layers that prevent the copper from contaminating other areas of the device, improve the adhesion of the copper film and enable electrodeposition to occur. Another application is wafer level packaging for deposition of copper to fill TSV 3D chip-to-chip connections. Applied offers special configurations of the Applied Raider system for these ECD applications. Physical Vapor Deposition PVD is a physical process in which atoms of a gas, such as argon, are accelerated toward a metal target. The metal atoms chip off, or sputter away, and are then deposited on the wafer. The Applied Endura PVD system offers various advanced metal deposition processes, including aluminum, aluminum alloys, cobalt, titanium nitride, tantalum/tantalum nitride, tungsten/tungsten nitride, nickel, vanadium and copper. Introduced 24 years ago, the Company's Applied Endura platform is the most successful metal deposition system in the history of the semiconductor industry. The Applied Endura CuBS (copper barrier/seed) PVD system is widely used by customers for fabricating copper-based chips. The system deposits a tantalum-based barrier film that prevents copper material from entering other areas of the device and then a copper seed layer that primes the structure for the subsequent deposition of bulk copper. The Applied Endura CuBS RFX PVD system extends cost-effective CuBS technology to the 2Xnm node. The Applied Endura Avenir™ RF PVD system sequentially deposits the multiple metal film layers that form the heart of the industry’s new, faster, metal gate transistors. The Applied Endura iLB PVD/CVD system enables customers to shrink their speed-critical contact structures for 20nm and below devices. The Applied Endura AmberTM PVD system uses copper reflow technology to achieve rapid, void-free fill of interconnect structures at virtually any device node. In 2014, Applied introduced the Endura VenturaTM PVD system, incorporating the latest industry-leading PVD technologies. The Ventura system supports the use of titanium in volume manufacturing as an alternative barrier material and expands Applied's comprehensive toolset for wafer level packaging applications, including through silicon vias, redistribution layers, and bump technology used to connect the die to the substrates. Applied’s Endura system has also been used for many years in back-end applications to deposit metal layers before final bump or wire bonding packaging steps are performed. Additionally, the Applied Charger® UBM PVD system, which is specifically designed for under-bump metallization (UBM) and other back-end processes, features linear architecture for reliable performance and very high productivity at a low cost per wafer. Etch Etching is used many times throughout the IC manufacturing process to selectively remove material from the surface of a wafer. Before etching begins, the wafer is coated with a light-sensitive film, called photoresist. A photolithography process then projects the circuit pattern onto the wafer. Etching removes material only from areas dictated by the photoresist pattern. Applied offers systems for etching dielectric, metal, and silicon films to meet the requirements of advanced processing.For etching silicon, the Applied Centris AdvantEdge™ Mesa™ system features eight process chambers for high wafer output and proprietary system intelligence software to assure every process on every chamber precisely matches. The system also saves on power, water and gas consumption, helping customers to lower operating costs and support their sustainable manufacturing initiatives. Chip manufacturers are also beginning to employ 3D architectures in advanced memory chips to provide higher-density storage capacity. These structures require the precise etching of exceptionally deep and narrow structures. To meet this industry requirement, Applied offers its Applied Centura AvatarTM dielectric etch system that can etch holes and trenches up to 80:1 depth-to-width aspect ratios. Also for 3D chip manufacturing, the Applied Centura Silvia® system is specifically designed for etching small, deep holes for TSV applications. Rapid Thermal Processing RTP is a process in which a wafer is subjected to rapid bursts of intense heat that can take the wafer from room temperature to more than 1,000 degrees Celsius in less than 10 seconds. A rapid thermal process is used mainly for annealing, which modifies the properties of deposited films. The Applied Centura Radiance®Plus and Applied Vantage® RadOx™ RTP systems feature advanced RTP technology with differing platform designs. While the multi-chamber Centura platform offers exceptional process flexibility, the streamlined two-chamber Vantage platform is designed for dedicated high-volume manufacturing. These single-wafer RTP systems are also used for growing high quality oxide and oxynitride films, deposition steps that traditional large batch furnaces can no longer achieve with the necessary precision and control. Applied’s latest RTP systems address the critical need for controlling wafer temperature to increase chip performance and yield. The laser-based Applied Vantage Astra™ millisecond anneal system abruptly raises the surface temperature of the wafer locally to modify material properties at the atomic level. The Applied Vantage Vulcan system, the first RTP system to heat the wafer entirely from the backside, brings a new level of precision and control to the anneal process, allowing chipmakers to produce more high-performance devices per wafer. Ion Implantation Ion implantation is a key technology for forming transistors and is used many times during chip fabrication. During ion implantation, wafers are bombarded by a beam of electrically-charged ions, called dopants, which change the electrical properties of the exposed surface films. These dopants are accelerated to an energy that permits them to penetrate the substrate at a precise quantity and depth. Dopant concentration is determined by controlling the number of ions in the beam and the number of times the wafer passes through the beam, while the depth of the dopants is determined by the energy of the beam. Ion implantation systems may also be used in other areas of IC manufacturing to modify the material properties of the semiconductor devices, as well as in manufacturing crystalline-silicon solar cells. Applied offers a line of single-wafer ion implantation equipment that covers the entire energy and current range required to manufacture advanced devices. The VIISta 3000XP implanter delivers the angle precision required for advanced high-energy applications, while the VIISta 900XP implanter provides medium current precision doping. The VIISta PLAD implanter enables manufacturers to rapidly implant high dopant concentrations over the entire wafer using a low-energy process that preserves sensitive circuit features in next-generation devices. The VIISta Trident high current ion implanter provides the precise dose and angle control needed for advanced transistor structures. Chemical Mechanical Planarization The CMP process removes material from a wafer to create a flat (planarized) surface. This process allows subsequent photolithography patterning and material deposition steps to occur with greater accuracy, resulting in more highly uniform film layers with minimal thickness variations. Applied has led the industry with its 300mm Applied Reflexion® LK system, with features such as integrated cleaning, film measurement and process control capabilities. Applied's latest CMP product, the Applied Reflexion LK PrimeTM, is a critical enabler for FinFET gate and 3D NAND staircase structures. Metrology and Wafer Inspection Applied offers several products for locating, measuring and analyzing defects and features on the wafer during various stages of the fabrication process. These systems enable customers to characterize and control critical dimension (CD) and defect issues, especially at advanced generation technology nodes. Critical Dimension and Defect Review Scanning Electron Microscopes (CD-SEMs and DR-SEMs) — Scanning electron microscopes (SEMs) use an electron beam to form images of microscopic features of a patterned wafer at extremely high magnification. Applied’s SEM products provide customers with full automation, along with the high accuracy and sensitivity needed for measuring very small CDs. The Applied VeritySEM® 4i+ metrology system uses proprietary SEM imaging technology to enable precise control of the lithography and etching processes, measuring CDs at a precision of less than 0.3nm. Applied’s OPC Check™ software for the VeritySEM system performs automated qualification of OPC-based (optical proximity correction) chip designs, significantly reducing mask verification time over conventional manual methods. DR-SEMs review defects on the wafer (such as particles, scratches or residues) that are first located by a defect detection system and then classify the defects to identify their source. The high-throughput, fully automatic Applied SEMVision™ Defect Analysis products enable customers to use this technology as an integral part of their production lines to analyze critical defects with industry-leading throughput. The Applied SEMVision G6 system, designed to accelerate time-to-yield for leading-edge chip manufacturing at the 1Xnm node and beyond and enhanced by the Purity™ Automatic Defect Classification (ADC), is the most advanced of the SEMVision family of products. Wafer Inspection — Using deep ultraviolet (DUV) laser-based technology, defects can be detected on patterned wafers (wafers with printed circuit images) as they move between processing steps. Defects include particles, open circuit lines, and shorts between lines. The Applied UVision® 6 wafer inspection system detects yield-limiting defects in the critical patterning layers of logic and memory devices. Mask Making Masks are used by photolithography systems to transfer microscopic circuit designs onto wafers. Since an imperfection in a mask may be replicated on the wafer, the mask must be virtually defect-free. Applied provides systems for etching and inspecting masks. Applied's Tetra™ systems have been used by mask makers worldwide to etch the majority of high-end masks including 28nm/14nm nodes. The Applied Centura Tetra EUV (extreme ultraviolet) Advanced Reticle Etch system fabricates leading-edge masks at 22nm and smaller dimensions. The Applied Aera3™ Mask inspection uses sophisticated aerial imaging technology that allows users to immediately see how the pattern on the mask will appear on the wafer, revealing only the defects most likely to print and significantly reducing inspection time. These systems also address the challenge of fabricating emerging EUV lithography masks.